Applications / Edge AI reference architecture

ReflexArc^™

An FPGA action co-processor
for real-time robots.
LEVCOM research & development

ReflexArc is LEVCOM’s R&D program exploring deterministic FPGA acceleration for vision-language-action robots. The reference architecture pairs GPU reasoning with a reconfigurable FPGA reflex loop for vision-language-action (VLA) robots. The GPU plans what to do. The FPGA translates that intent into responsive motion, with independent hardware safety supervision.

Xilinx + Altera FPGA platforms

Discuss ReflexArc

System 2 / Brain

GPU planner

The vision-language planner interprets the scene and sends a compact conditioning latent when the plan changes.

5–10 Hz planning target

System 1 / Spinal cord

FPGA action expert

On-chip weights and context feed a fast reflex loop. Reconfigurable operators support flow-matching and diffusion action heads.

50–500 Hz reflex target

System 3 / Guardian

Hardware safety

Independent checks monitor joint limits, sensor validity and faults. A command gate can pass, clamp or stop actuator commands.

500–2,000 Hz monitoring target

ReflexArc architecture: a GPU planner sends context to an FPGA action expert, while a separate hardware guardian supervises motor commands. — System architecture Open diagram to view full size ↗

Latent-stationary dataflow

Load context once.
Reuse it every reflex step.

The planner’s latent stays constant between re-plans. ReflexArc keeps that context, action-expert weights and working state on-chip for repeated control steps, reducing off-chip memory transfers. The design targets near-zero off-chip traffic within the reflex loop, while hardware safety checks run independently.

Explore memory traffic and control timing

Timing diagram showing planner context reused across faster reflex steps and independent safety checks, with reduced DRAM traffic. — Latent reuse and memory traffic Open diagram to view full size ↗

Hardware platforms

Xilinx and Altera.
One ReflexArc approach.

ReflexArc’s heterogeneous architecture combines NVIDIA Jetson GPU planning with FPGA processing and control. The platform designs span Xilinx KV260 and Altera Agilex 5, adapting the implementation to the robot’s sensors, actuators and integration needs.

Xilinx KV260 + NVIDIA Jetson Orin

The demo platform assigns real-time processing, motion control and safety to the Xilinx FPGA, with VLA reasoning on the Jetson.

Xilinx KV260 and NVIDIA Jetson Orin platform with sensor inputs, motion control and robot interfaces. — Xilinx platform View full size ↗

Altera Agilex 5 + NVIDIA Jetson AGX Orin

The proposed Altera platform pairs an Agilex 5 E-Series development kit with Jetson AGX Orin. The GPU–FPGA interface is under evaluation.

Proposed Altera Agilex 5 and Jetson AGX Orin architecture connecting sensors, FPGA control and actuators, with the GPU-to-FPGA interface to be decided. — Altera platform View full size ↗

Performance figures in this section and the diagrams describe design targets and architectural estimates. Results depend on the model, FPGA resources and system configuration.

ReflexArc™